1. Field of the Invention
The invention relates to a DRAM cell arrangement and a method for its production. More particularly, the invention relates to a vertically structured DRAM cell arrangement.
2. Description of the Related Art
In DRAM cell arrangements, i.e. memory cell arrangements with dynamic random access, what are known as single transistor memory cells are used almost exclusively. A single transistor memory cell comprises a selection transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electrical charge representing a logical quantity of 0 or 1. By activating the selection transistor via a word line, the information can be read out via a bit line.
Usually, a first source/drain region of the selection transistor is connected to the storage capacitor, and a second source/drain region of the selection transistor is connected to the bit line. A gate electrode of the selection transistor is connected to the word line (cf. e.g. S.M.Sze Semiconductor Devices, ATandT Bell Laboratories, Murray Hill, N.J. 1985, p. 487, FIG. 18a).
Since the memory density increases from generation to generation, the surface of the single transistor memory cell must be reduced from generation to generation. As such, reducing the dimensions of the memory cell is limited by the minimal structural size,  that can be produced in the respective technology. In addition, the memory cell may be altered. Thus, up to the 1 MBit generation, both the selection transistor and the storage capacitor were realized as planar components. Since the 4 MBit memory generation, a further surface reduction has had to occur by means of a three-dimensional arrangement of the selection transistor and storage capacitor.
One option is to design the storage capacitor in a trench instead of in a planar fashion (see K. Yamada, xe2x80x9cA deep trenched Capacitor technology for 4 Mbit DRAMsxe2x80x9d, Proc. Intern. Electronic Devices and Materials IEDM 85, p. 702). However, the creation of such a buried storage capacitor is expensive. Also, capacitor dielectrics with high dielectricity constants cannot be used, since their deposition is only possible in essentially planar surfaces.
German Patent Document No. 195 19 160 C1 proposes a DRAM cell arrangement in which the storage capacitor is created over the selection transistor, and the bit line is buried in the substrate. Since the storage capacitor is created at a surface of the substrate, capacitor dielectrics with high dielectric constants can be used. Each memory cell has a protuberant semiconductor structure having a first source/drain region. A channel region is positioned underneath the first source/drain region and a second source-drain region is positioned underneath the channel region. The protuberant semiconductor structure is surrounded annularly by a gate electrode.
Semiconductor structures of memory cells are arranged in rows and columns. Neighboring rows of the semiconductor structures are translation-symmetrical in relation to an axis extending parallel to the columns. In order to create word lines in a self-justified fashion, i.e. without using masks that need to be justified, the intervals between semiconductor structures that are arranged along the columns are smaller than intervals between semiconductor structures that are arranged along the rows. The semiconductor structures are surrounded by a grid-shaped depression. The word lines emerge by the deposition and etchback of conductive material in the form of gate electrodes that are situated adjacently along the columns. The buried bit line is created from a doped layer, which is structured in a strip-shaped fashion by trenches filled with insulating material. The trenches are created with the aid of a strip-shaped first mask.
With the aid of a strip-shaped second mask, whose strips extend perpendicular to the trenches, depressions are created between the trenches by the etching of semiconductor material. The depressions do not cut through the doped layer, so as not to cut through the bit line. The semiconductor structures emerge from a layer sequence by the creation of the trenches and the depressions. The depressions are also filled with insulating material. The insulating material is subsequently etched back, the semiconductors are thereby exposed and the grid-shaped depression emerges. Due to the common etching of the insulating material in the depressions and of the insulating material in the trenches, the floor of the grid-shaped depression is flat, which is essential for the self-justified creation of the word lines.
To increase the packing density, the first mask is created in that strips having a width F are first created by a photolithographic process. The strips are widened by the deposition and etchback of material. A distance between neighboring strips of the first mask is thus less than F. The strips of the second mask are created with the width F, by reason of which the above cited conditions regarding the distances between the semiconductor structures are satisfied. The memory cell""s surface area is 4F2. The first source/drain region acts as the first capacitor electrode of the storage capacitor. A second capacitor electrode is created by the whole-surface deposition of conductive material over the capacitor dielectric.
In U.S. Pat. No. 4,630,088 it is suggested that the storage capacitor be connected between a first source/drain region of the selection transistor and the bit line. Each memory cell has a protuberant semiconductor structure which is surrounded by a gate electrode annularly. The memory cells are arranged off-set to one another diagonally with respect to a word line direction. The storage capacitor includes the first source/drain region, a part of a whole-surface-deposited capacitor dielectric, and a part of the bit line. The first source/drain region, a channel region and a second source/drain region of the selection transistor are arranged above one another in layers.
The invention is based on the problem of proposing a DRAM cell arrangement which, given a high packing density, can be produced with a smaller processing outlay than previously available. A production method for such a DRAM cell arrangement is also proposed.
In an inventive DRAM cell arrangement, a semiconductor substrate includes a number of projections arranged in rows and columns. Neighboring rows of the projections are translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each projection has at least one first source/drain region and one channel region of a vertical selection transistor, the channel region being arranged under the first source/drain region. The projection can also have a second source/drain region of the selection transistor. The projection is provided with a gate dielectric at least in the area of the channel region. Each of the projections is surrounded annularly by a gate electrode of the selection transistor. A word line is formed by gate electrodes which neighbor one another along an x-axis parallel to the rows and which are situated adjacently. A first capacitor electrode of the storage capacitor is electrically connected to the first source/drain region. The first capacitor electrode is cut in two by a capacitor dielectric of a second capacitor electrode of the storage capacitor, which is arranged over the first capacitor electrode. The second capacitor electrode is electrically connected to a bit line which extends essentially parallel to the columns. The storage capacitor is connected between the first source/drain region and the bit line. The second source/drain region is buried in the semiconductor substrate.
In order to connect the second source/drain regions of selection transistors to a common potential, it is advantageous to connect at least a few of them to each other.
Since the second source/drain regions are not connected to bit lines, they can be parts of a continuous layer which does not need to be structured. A mask is not necessary for the creation of the second source/drain regions, which reduces the processing outlay.
Since not only the bit line, but also the storage capacitor is created at a surface of the semiconductor substrate, the creation of structures that are buried in the semiconductor substrate is avoided, which also reduces the processing outlay.
The utilization of capacitor dielectrics with high dielectric constants is possible, since the storage capacitor is not created in a deep trench.
An advantage of the inventive memory cell arrangement is that xcex1-particles which emerge in the semiconductor substrate reach the bit line, which is arranged at the surface of the semiconductor substrate, and the storage capacitor having only a low probability, so that the probability of falsifying information is therefore low.
The projections are preferably created by a structuring of a layer sequence. To this end, a first layer which is doped by a first conductivity type is created; a second layer which is doped by a second, opposite conductivity type is created over this layer; and a third layer which is doped by the first conductivity type is created over the second layer. The first layer, the second layer, and the third layer can be created by implantation of the semiconductor substrate and/or by epitaxy which is doped in situ. If a layer is created by epitaxy doped in situ, then the semiconductor substrate is enlarged by this layer.
To simplify the processing, it is advantageous if the projections are created by etching with only one mask. A grid-shaped depression is thus created which is divided at least by the third layer and the second layer. Thus, all the vertical dimensions of each projectionxe2x80x94i.e. perpendicular to the semiconductor substratexe2x80x94are equal. In other words, all the sides of each projection have the same length perpendicular to the semiconductor substrate. Alternatively, parallel first trenches can be created in a first (etching) step, and second trenches, which extend transversely to the first trenches, can be created in a second (processing) step.
First source/drain regions of the selection transistors emerge from the third layer as parts of the projections, and channel regions of the selection transistors emerge from the second layer. The grid-shaped depression or the first trenches and the second trenches reach into the first layer. The second source/drain regions are parts of the first layer.
To simplify the processing, it is advantageous to produce the grid-shaped depression or the first trenches and the second trenches optimally flat in that the first layer is not divided.
To simplify the processing, it is advantageous if the word lines are created self-justified. Self-justified creation is possible, for example, if intervals between projections which are arranged along the columns and are parallel to the column direction, are greater than intervals between projections which are arranged along the rows and are parallel to the row direction. To create the word lines, conductive material is deposited in a conformal fashion, whereby a wave-shaped conductive layer emerges. Valleys of the waves of the conductive layer extend parallel to the rows. The conductive material fills the space between the projections which are arranged along the rows, while it does not fill the space between the projections which are arranged along the columns. The conductive layer is etched back anisotropically until parts of the conductive layer which are arranged above the first source/drain regions and between the neighboring projections along the columns are removed. Thus, the word lines emerge from the conductive layer. The word lines are not connected in the column direction. Since the conductive material fills the space between the projections which are arranged along the rows, there is relevant conductive material between the projections which are arranged along the rows even subsequent to the etchback of the conductive material. At the sides of the projections which are parallel to the direction of the rows, the word lines or the gate electrodes take the form of spacers.
To increase the packing density, it is advantageous if the distances between the projections which are arranged along the rows are smaller than F. To create the projections, a mask can be used which is enlarged by spacers in the row direction. For example, first parts of the mask are created in that material is deposited and structured by a strip-shaped first mask made of photosensitive resist, the strips of which extend parallel to the columns. Additional material is subsequently deposited and etched back, whereby spacer-shaped second parts of the mask emerge at the sides of the first parts of the mask. The first parts and the second parts of the mask are structured with the aid of a strip-shaped second mask made of photosensitive resist, the strips of which extend parallel to the rows, whereby the mask emerges. The widths of the strips of the first and second photosensitive resist masks as well as the distances between the strips of the first photosensitive resist mask and the distances between the strips of the second photosensitive resist mask are preferably equal to F. The described steps guarantee that the intervals between the projections which are arranged along the rows are smaller than the intervals between the projections which are arranged along the columns.
To simplify the processing it is advantageous if the first source/drain region coincides with the first capacitor electrode. Alternatively, the first capacitor electrode is created over the first source/drain region by the structuring of an additional conductive layer, for example.
To simplify the processing, it is advantageous if the second capacitor electrode is part of the bit line. To this end, conductive material can be deposited over the capacitor dielectric and structured in a strip-shaped fashion.
To enlarge the signal of the storage capacitor, it is advantageous if the capacitor dielectric is created from a material with a high dielectric constant, such as perovskite (e.g. BaxSr1 xe2x88x92xTiO3, SrBi2Ta2O3, PbZrTiO3) or Ta2O5. Since such materials are preferably deposited on flat surfaces, it is advantageous to create an insulating structure subsequent to the creation of the gate electrodes in that insulating material is deposited and planarized until the first source/drain regions are exposed. The capacitor dielectric is then deposited over the first source/drain regions, which act as first. capacitor electrodes.
The semiconductor substrate is a silicon substrate or an SOI substrate.